Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits (ICs) that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the ICs. The ICs include field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs).
As technology nodes shrink, in some IC designs, there has been a desire to replace the typically poly-silicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming the metal gate electrode is termed a “gate last” process in which the final metal gate electrode is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
FIG. 1 shows a top view of a semiconductor device 100 comprising a conventional interconnection structure 110 fabricated by a “gate last” process. The semiconductor device 100 comprises an n-type MOSFET (nMOSFET) 100n and a p-type MOSFET (pMOSFET) 100p. The nMOSFET 100n is formed from the first gate electrode 110n overlying the channel region of the active area 104n. The pMOSFET 100p is formed from the second gate electrode 110p overlying the channel region of the active area 104p. The first gate electrode 110n and second gate electrode 110p are electrically coupled to each other and collectively hereinafter referred to as an interconnection structure 110. The interconnection structure 110 is electrically coupled to a voltage source via a contact 130.
FIGS. 2A-C show cross-section views taken along the respective lines of FIG. 1. FIG. 2A illustrates a cross-sectional view of the second gate electrode 110p of the pMOSFET 100p taken along the line a-a of FIG. 1. The second gate electrode 110p may comprise a first barrier metal layer 112p, a p-type work function metal layer 114p, a second barrier metal layer 116p, and a signal metal layer 118p. FIG. 2B illustrates a cross-sectional view of the first gate electrode 110n of the nMOSFET 100n taken along the line b-b of FIG. 1. The first gate electrode 110n may comprise a first barrier metal layer 112n, a n-type work function metal layer 114n, a second barrier metal layer 116n, and a signal metal layer 118n. FIG. 2C illustrates a cross-sectional view of an interconnection structure 110 comprising both the first gate electrode 110n of the nMOSFET 100n and the second gate electrode 110p of the pMOSFET 100p taken along the line c-c of FIG. 1. A contact 130 is deposited on the interface between the first gate electrode 110n and the second gate electrode 110p. 
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, it is difficult to achieve a uniform contact resistance for all CMOS devices 100n/100p because shifts in the position of the contact 130 to the interconnection structure 110 causes shifts in the contact resistance to the CMOS devices 100n/100p. The unstable contact resistance may provide unstable voltage supply through the contact 130 to the interconnection structure 110, thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what is needed is an interconnection structure in which the contact resistance is less sensitive to process variation.